The fabrication of semiconductor devices is a complex process that varies from one device to another device, depending on design specifications. For this and many other reasons, the manufacture of semiconductor devices requires careful monitoring to ensure adequate quality control, which, in turn, allows a fabrication facility to maintain acceptable product yields.
As one such monitoring process, wafer screening is performed during the semiconductor device fabrication process to monitor the function and performance of chips fabricated on the wafer. In particular, wafer screening criteria consists of a rigid set of predefined kerf parameters that are independent of the chips, and are defined by a design manual and wafer acceptance criteria (WAC). For example, the WAC are designed in order to determine acceptance of the wafer. This acceptance can be defined by any number of parameters that an inline kerf structure is configured to measure. The measurements of the inline kerf structure may then be specified (e.g., spec'ed) to the WAC to determine acceptance of the wafer. Using the rigid set of predefined kerf parameters, a set number of inline kerf structures are tested, which are used in a statistical analysis. If a certain number of these inline kerf structures fail, then the entire wafer will be discarded, regardless of individual chips meeting performance standards. This can result in lower yields.
More specifically, selecting or sorting the chips based on a fixed set of WAC may cause a circuit limited yield for the chips since the predefined kerf limits may not accurately reflect the chip performance. For example, the performance of the inline kerf structure does not accurately reflect the performance of each chip on the wafer, and miscorrelation of kerf measurements to chips can result in poor selection of customer dies. The largest contributor to this miscorrelation issue is systematic kerf-to-chip offset. Factors influencing this kerf-to-chip offset include: PC density (perimeter density or Pden), layout differences between the kerf structure and the chip, n-well stress factors, shallow trench isolation (STI) factors, across chip line width variation (ACLV), front end of line (FEOL) variations, back end of line (BEOL) variations, etc. Dies (chips) picked based entirely on kerf data (in specification) can result in out of specification chip performance (circuit limited yield) due to this kerf-to-chip offset.
To complicate matters, several different designs (e.g., chips) can be manufactured on a single multi-project wafer (MPW) process. In this scenario, each chip can be different with the on-chip FET performance varying depending on the physical attributes of the chip design. In such a scenario, ensuring quality and yield becomes exceptionally complicated, taking into account the many different designs that may be on a single wafer.
For example, it is known that each reticle (design for a die or chip) has a line monitor (i.e., inline kerf structures). Taking into account that the wafer may include 60 to 70 reticles depending on wafer requirements, there can be 60 to 70 or more line monitors (i.e., inline kerf structures) on a single wafer. Generally, testing is not performed on all of these inline kerf structures; instead, the fabrication facility will test only a sample of these inline kerf structures and, using statistical analysis, will determine whether the entire wafer has passed. However, even if the wafer passed or failed, the tested inline kerf structures may not be deterministic of all of the dies (e.g., chips) on the wafer, leading to yield issues.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.